Header menu link for other important links
15–4 Approximate Compressor Based Multiplier for Image Processing
Swathi Krishna T.U, Riyas K.S, Premson Y,
Published in IEEE
Pages: 671 - 675
Compressor adders have lesser critical delay than normal adders, so that they are suitable in multiplier architectures. In multiplication operation, compressors are used for the reduction of partial products to decrease the delay and power dissipation. In image processing operations multiplication is the common operation. In these applications accurate computing is not essential and it can produce meaningful results even it has low accuracy. Approximate computing is used in these image processing and multimedia applications since it is less complex and has low power consumption. Compressor outputs are approximated to produce approximated compressor. Higher bit multiplications require large size compressors. Here four different designs of approximate 15-4 compressor are described. 16 bit multiplier is designed using this compressor. Multiplication of two images on pixel by pixel basis is done with this multiplier. © 2018 IEEE.
About the journal
JournalData powered by Typeset2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI)
PublisherData powered by TypesetIEEE
Open Access0