One of the most important hardware blocks in processors is the multiplier circuit module. Area, power, and delay rule as primary factors deciding VLSI design methodologies. The work presented in this paper focuses on these three factors using Vedic multiplication approach and gate-diffusion input (GDI) logic. The ancient system of Indian mathematics being the Vedic mathematics, rediscovered from the Vedas, is more simplified, faster and accurate as compared to normal multiplication methods. The primary advantage of gate-diffusion input (GDI) logic is helping in reduced transistor count. Hence, the combination of these approaches of Vedic multiplication implemented using GDI logic results in reduced propagation delay time, lower power consumption, and less silicon area. In this paper, the proposed 2-bit Urdhva cell used is implemented using AND gate, XOR gate, and an inverter unlike the existing literature in which it is implemented using two half adders. The results are validated for the comparative advantages of our approach. The circuit simulations are carried out using UMC 90 nm technology nodes in Cadence Virtuoso. © 2021, Springer Nature Singapore Pte Ltd.