In this paper, an 8-bit asynchronous wave-pipelined arithmetic logic unit has been modified with set of 8 arithmetic and 12 logical operations. All the internal modules have been modified in order to reduce power and latency by using ASIC semi-custom design flow in cadence® environment using gpdk-180-nm technology. This modified design has achieved reduction in power by 45%, reduction in delay by 19%, reduction in area by 43%, reduction in cell count by 49% as compared to the existing ALU. © 2018, Springer Nature Singapore Pte Ltd.