The prescaler is primarily used in phased locked loop (PLL) to generate higher reference frequency for the loop, which supplies more samples per unit time to the phase detector to attain better frequency stability. This paper is first to present a Modified Extended True Single Phase Clock (METSPC) based 2/3 prescaler design. The METSPC-FF is fully investigated across all the process corners for power consumption and delay along with its functionality for GHz operations. Both ETSPC and METSPC are compared to find that the PDP of METSPC is 64.96% better than ETSPC. Thus using METSPC enhances the operating performance of the prescaler. A multimodulus 32/33/39/40/47/48 prescaler is proposed and its operation is verified over all PVT variations with a max. frequency of 6GHz. Simulation is performed in TSMC 90 nm technology using CADENCE SPECTRE simulator at supply voltage of 1.1V. © 2013 IEEE.