The prescaler is primarily used in phased locked loop (PLL) to generate higher reference frequency for the loop, which supplies more samples per unit time to the phase detector to attain better frequency stability. This paper is first to present a Modified Extended True Single Phase Clock (METSPC) based 2/3 prescaler design. The METSPC-FF is fully investigated across all the process corners for power consumption and delay along with its functionality for GHz operations. Both ETSPC and METSPC are compared to find that the PDP of METSPC is 64.96% better than ETSPC. Thus using METSPC enhances the operating performance of the prescaler. A multimodulus 32/33/39/40/47/48 prescaler is proposed and its operation is verified over all PVT variations with a max. frequency of 6GHz. Simulation is performed in TSMC 90 nm technology using CADENCE SPECTRE simulator at supply voltage of 1.1V. © 2013 IEEE.

Kittur Harish Mallikarjun

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Mohammed Zackriya V

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

90nm CMOS Low Power Multimodulus 32/33/39/40/47/48 Prescaler with METSPC Based Logic

2013 Third International Conference on Advances in Computing and Communications

The Clock Divider circuit has found immense application in Multiple Clock Domain (MCD) systems like ASICs, SoC and GALS. In MCD systems, we generate many clock signals of various frequencies from a high frequency clock by frequency division. Power is an important parameter to be minimized since the nodes in a clock divider circuit will toggle at clock frequency. In this paper, we present a low power hybrid clock divider circuit which can take an input frequency up to 6 GHz and perform frequency division. The divider is hybrid because it uses two different flip flops - a Modified Extended True Single-Phase Clock flip flop (METSPC-FF) and a self blocking FF (SBFF).The METSPC-FF is fast enough to divide a GHz frequency, but consumes more power when compared to SBFF, while the SBFF is relatively slow but consumes less power compared to METSPC. We analyze the performance of these 2 FFs across PVT variations and implement them in a clock divider circuit. Our clock divider circuit consumes 149.56 μW power for 'divide by' 8 operation on a 6 GHz clock. Simulation of these flip flops in TSMC 90 nm technology using CADENCE SPECTRE simulator shows that they are very energy efficient and hence can be used for other high speed applications without compromising on the power. © 2013 IEEE.

2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT)

Low power, high speed hybrid clock divider circuit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

A Low-Power Single-Phase Clock Multiband Flexible Divider

IEEE Journal of Solid-State Circuits

The Speed–Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers

2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

Development of 90Nm InGaAs HEMTs and Benchmarking Logic Performance with Si CMOS

Journal	Data powered by Typeset2013 Third International Conference on Advances in Computing and Communications
Publisher	Data powered by TypesetIEEE
Open Access	No