In this paper, a novel current reference circuit using a single beta multiplier is proposed. To achieve better process compensation, some identical series connected transistors with optimum aspect ratios are proposed for the generation of both PTAT and CTAT currents. Diode connected cascode transistors are proposed for the generation of the bias voltage for these transistors to reduce the area and power dissipation. The proposed current reference circuit is designed and implemented for a current of 100 nA at 50°C, using UMC 180nm CMOS process technology and simulated. The proposed circuit has a lower temperature coefficient (124.5 ppm/°C in the range 0°C - 100°C), lower line sensitivity (0.35%/V over a supply voltage range of 1.253 V) and lower process variation of |0.3%| compared to those reported in the literature. It requires lower total current as well as area and has the best figure of merit of 1.645 %. © 2019 IEEE.