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A 4-bit 9 KS/s Distortionless Successive Approximation ADC in 180-nm CMOS Technology
Dipu P, Saidulu B, Aravind K, Raj J.S,
Published in Springer India
Volume: 324
Pages: 55 - 63
In recent years, analog-to-digital converters are the crucial part of many applications. In this paper, we proposed a 1.8 V capacitor-array-based successive approximation ADC. This SAR ADC uses bootstrapped switch to decrease distortion, and comparison is done using a pre-amplifier preceding a latched comparator. A 4-bit SAR ADC with high resolution was designed in 180-nm CMOS process. This paper aims at describing the design of a discrete-component, successive approximation register analog-to-digital converter (SAR ADC). The performance evaluation was done using Cadence ADE tool. © Springer India 2015.
About the journal
JournalData powered by TypesetAdvances in Intelligent Systems and Computing Artificial Intelligence and Evolutionary Algorithms in Engineering Systems
PublisherData powered by TypesetSpringer India
Open AccessNo