Inverter based comparators are proposed in the literature for medium speed ADCs with low power and low area requirements. The comparator is succeeded by a buffer in order to boost the gain of the comparator. This requires an additional delayed clock which limits the speed of the ADC. To overcome this limitation, a modified inverter based comparator which uses a single clock signal is proposed in this paper. The analog input is converted to gray codes first and then to binary codes. It dispenses with power hungry thermometer to binary code converter. For evaluating its efficacy, a 4-bit ADC using the proposed technique is implemented in UMC 0.18μm CMOS technology at a supply voltage of 1.8 V. The proposed ADC achieves a maximum sampling rate of 100 MS/s for an input signal with 1.8 V swing and has a power consumption of 1.08 mW. The power dissipated by the proposed ADC is lower compared to those reported in the literature. The proposed ADC exhibits INL of 1.36 LSB, DNL of 1.04 LSB, SNDR of 23.59 dB and ENOB 3.62 bits respectively. It has a better FoM of 0.87 pJ/conversion step. © 2015 IEEE.