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A binary high speed floating point multiplier
Konduri arun,
Published in IEEE
Pages: 316 - 321
Objective: To implement an algorithm for improving the speed of Floating Point Multiplication. Methods/Statistical analysis: Recursive Dadda algorithm is used for implementing the floating point multiplier. IEEE 754 single precision binary floating point representation is used for representing Floating Point number. For the multiplication of mantissa Carry Save multiplier is replaced by Dadda multiplier for improving the speed. Using Verilog HDL multiplier is implemented and it is targeted to Xilinx vertex-5 FPGA. Improvements: The speed of operation is increased compared with Carry Save Multiplier. The multiplier which we developed handles both overflow and underflow cases. © 2017 IEEE.
About the journal
JournalData powered by Typeset2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)
PublisherData powered by TypesetIEEE
Open AccessNo