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A counterbalancing technique for skew and power management of clock tree
M. Jayakumar, , V. Prakash, A.S. Ponraj
Published in Asian Research Publishing Network
Volume: 13
Issue: 8
Pages: 2713 - 2719
Many Integrated Circuits (or ICs) consisting of sequential logic use a clock signal for synchronizing different components of the circuit. The clock tree distributes the clock signals from its source to all the components and hence, any uncertainty in the arrival times of the clock signals can intensely limit the performance of the whole circuit. Generating the clock tree network with minimum skew and power consumption plays a vital role in digital IC design. On this research work, the three methods i) low swing ii) buffer upsizing and iii) polarity assignment techniques has been used together to achieve minimum power and skew in a clock tree network. It has been observed that applying polarity assignment technique after the low swing and buffer upsizing techniques reduces the clock tree network delay to 25% and power consumption of the clock tree network lies between first two techniques and hence this method gives counterbalanced clock tree network with respect to skew and power consumption. The research work has been carried out using tsmc 180nm technology library, Cadence® Virtuoso®, Cadence® Layout editor and Cadence® Assura® tools. © 2006-2018 Asian Research Publishing Network (ARPN).
About the journal
JournalARPN Journal of Engineering and Applied Sciences
PublisherAsian Research Publishing Network