Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one. © 2016 IEEE.