In this research work, low power and low area based multiplier architecture is proposed for high speed applications. There are a few enhancement made to the conventional shift and add multiplier architecture, the normal adder for addition has been replaced by the Error Tolerant[ET] concept for designing the adder and activating the adder cells by current multiplication bit of the multiplier constant. In the normal design, carry propagation dissipates the significant amount of dynamic power consumption. In contrast to the existing architectures, in this proposed architecture the multiplexer is removed and when the multiplicand has a zero as a bit the adder is bypassed. Shifting the partial products and multiplier bits is done by using the down counter. The proposed ET shift and add multiplier is synthesized in the XILINX software and simulated in ModelSim. The result for 8x8 multiplier shows the proposed design reduces the power consumption and delay by 55mw and 49ns respectively compared to the existing one. The area, power, and delay optimization is achieved by using the error tolerant shift and add multiplier. Hence making it suitable for image processing application because minimum amount error is tolerable. © IAEME Publication.