Multipliers plays a vital role in the field of digital processing of information especially signal and image. The key benefit of 64 bit multiplier is high precision computation but it has to be faster as well. In this paper, we have designed a modified 64 bit Wallace multiplier. The designed multiplier reduces the number of half adders which are mainly used in the reduction phase of multiplier and also they do not contribute in the reduction of partial products. For the entire multiplication process we have used only 38 half adders. The multiplier is designed using Verilog-HDL and implemented using TSMC 45nm technology. It is found that the designed multiplier has reduced number of half adder in each stage and it consumes 15.22 mW at 166 MHz.