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Proceedings Article
A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimationPublished in IEEE
2013
Topics: Sum of absolute differences (62)%62% related to the paper, Quarter-pixel motion (57)%57% related to the paper, Motion estimation (56)%56% related to the paper, Carry-save adder (55)%55% related to the paper and Gate count (55)%55% related to the paper
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About the journal
| Journal | Data powered by Typeset2013 International Conference on Emerging Trends in Communication, Control, Signal Processing and Computing Applications (C2SPCA) |
|---|---|
| Publisher | Data powered by TypesetIEEE |
| Open Access | 0 |
Authors (2)
Aarthi G- A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimation
- Applying regression models to calculate the Q factor of multiplexed video signal based on Optisystem
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- Aperture averaging effects on the average spectral efficiency of FSO links over turbulence channel with pointing errors
Jayakrishnan P- 2-Dimensional systolic architecture for H.264/AVC variable block size motion estimation
- Implementation of non-linear pipelined floating point adder
- Implementation of adder structure with fast carry network for high speed processor
- Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture
