In finance transactions and tax calculation the binary coded adder (BCD) are preferred than binary adders. The conventional BCD adder has two four-bit binary adders. One is used for finding the binary-sum and the other for the decimal sum. The conventional BCD adder has a huge carry delay due to the presence of a four-bit binary adder in the binary-sum stage. The technique proposed in this work provides a solution for this problem. In the proposed design, only one four-bit binary adder is used at the end of the process. A new method is proposed for determining the decimal carry of the BCD adder. The feature of the proposed design is that the decimal carry is calculated in two gate delays, except for the first digit. The synthesis results show that the proposed circuit generates the final sum around 3.5 times faster than conventional 32-digit BCD adder. The proposed design provides an area overhead of 0.68 times the conventional, while the power consumption remains the same. © BEIESP.