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A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
B.S. Paul S, , L. Gopalakrishnan
Published in Elsevier B.V.
2021
Volume: 76
   
Pages: 69 - 75
Abstract
In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to reduce area and latency. Moreover, normalised energy consumption and area delay product are reduced by 32%, and speed is increased by 5.2 times compared to prior works. Further, the fixed-point word-length is optimised to minimise the area without affecting the accuracy. © 2020 Elsevier B.V.
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JournalData powered by TypesetIntegration
PublisherData powered by TypesetElsevier B.V.
ISSN01679260