This paper presents about the design of a low power 10-bit 50-M sample /sec Sample and Hold amplifier. A sample and hold amplifier (SHA) acts as a front end block for an Analog Digital Circuit (ADC). To realize a low power SHA, a power efficient Operational Tran-conductance Amplifier (OTA) is to be designed and used. In the literature, many topologies of OTA are proposed for low power. In this paper, an Improved Recycling Folded Cascade (IRFC) OTA existing in the literature is used for realizing SHA and is proposed. In addition to this the SHA includes bottom plate sampling and bootstrap switch to reduce the non-linear distortion. The IRFC OTA used in the design of SHA is implemented using TSMC 90 nm Process. It achieves a DC gain of 73 dB, Unity Gain Bandwidth (UGB) of 70 MHz and with a phase margin of 63 degrees. The proposed SHA is designed and simulated using spectre simulator. From the simulation, it is noted that the SHA achieves a Spurious Free Dynamic Range (SFDR) of 63.44dB and SNDR of 60.6dB for a sampling frequency of 50MS/s with a peak-peak voltage of 1.2 Volts. The S/H circuit consumes 0.44mW of power. © 2018 Copyright is held by the owner/author(s).