An adder is one of the main components in many digital devices, DSP processors, etc. Leakage power reduction and area have become important factors in designing recent VLSI circuits. As the technology is constantly scaling down, threshold voltage of transistors is also reduced, thereby making the static power dissipation high. In this paper a low power 10T full adder is designed in 45 nm complementary pass transistor technology. Power dissipation and delay are compared with the conventional 28 transistor full adder, proposed 10 transistor full adder, Multi Threshold CMOS (MTCMOS) based 28 transistor full adder and proposed Multi Threshold based 10 transistor full adder. Compared to the conventional 28 transistor full adder, the proposed design shows power dissipation is reduced by 99.528% and Power Delay Product (PDP) by 99.913%. The proposed circuit reduces the area used by 64% accompanied with high speed of operation. © 2016 IEEE.
|Journal||Data powered by Typeset2016 11th International Conference on Industrial and Information Systems (ICIIS)|
|Publisher||Data powered by TypesetIEEE|