Phase Locked Loop (PLL) based frequency synthe-sizers are widely used to generate spectrally pure clock references for the cores in System-on-Chips (SoCs). Fractional- N PLL has evolved from the basic integer-N PLL to enable high resolution in output frequency. A Dual Modulus Prescaler (DMP) forms an integral part of the feedback circuitry to achieve fractional 'divide-by' ratios. It is also used to scale down the output frequency of Voltage Controlled Oscillator (VCO) for phase and frequency comparisons. Since DMP works at the highest frequency in design strenuous feedback block of a PLL, numerous researchers have proposed various techniques to reduce the power consumption of DMPs. In his paper we first propose a low power FF of True Single Phase Clock type which is then used to construct a DMP. Our proposed 2/3 prescaler works effectively till 12 GHz. Since PLL demands high accuracy, we also simulate our design across the PVT (Process, Voltage, Temperature) variations upto 5 GHz to verify its suitability for frequency synthesis. Our DMP consumes power lesser than 100 W while dividing a 5 GHz clock which is energy efficient compared to others in recent literature. © 2014 IEEE.