In this article, a novel low power adiabatic circuit, namely the modified complementary pass transistor logic (MCPAL) powered by a four phase power clock supply, is proposed. The important features of the proposed logic are its low leakage power, glitch free output, and lower switching noise compared to the counterpart circuits found in the literature. Efficiency of the proposed adiabatic logic is validated by comparing with the basic inverter circuits designed using 2N2P, 2N-2N2P, PFAL, CPAL, and DCPAL type of adiabatic logic circuits. Secondly, the utilization of self-aligned double gate FinFETs in the design of MCPAL is also studied, with the use of an inverter and 512 stages of cascaded inverters implemented using 32 nm FinFET and 32 nm lower technology MOSFET by employing their corresponding BSIM model files. The circuits are designed and simulated in Cadence Virtuoso® tool environment through an operating frequency range from KHz to GHz. © Springer Nature Singapore Pte Ltd. 2018.

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Bhuvana B.P

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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A Novel Adiabatic Logic for Low Power VLSI Circuit Design and Power Optimization Using FinFET

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

Design and Analysis of FinFET Based CSCPAL Low Power Adder

Novel area and energy efficient 2N-N-2P adiabatic logic with less leakage, switching noise and glitch free outputs is presented. FinFETs replace MOSFET for reduced short channel effects, lower leakage, less area and operating speeds. 2N-N-2P logic is validated using 32nm MOSFET and FinFET models and by comparison with 2N-2N2P and PFAL. FinFET circuits are compared with CMOS counterparts using benchmark inverters, Full adder, 512 inverter cascades and 4-bit CLA. The analyses also authenticate better performance under process parameter variations and demonstrate advantages of the use of FinFET for all the Evaluate, Hold and Recovery phases. © 2017 The Author(s).

Fulltext

Procedia Computer Science

Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET

The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.

Journal of Circuits, Systems and Computers

PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES

This paper presents Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) that can operate with greater functionality, larger fan-in and high energy efficiency. It is a diode free and dual rail logic operated by four phase power clock for the adiabatic pipeline. Less complex with differential cascode structure and fewer numbers of transistors, the pre-resolving feature for the complementary inputs achieves reduction in latency, significant drop in the switched capacitance that realizes power efficiency, better silicon area efficiency, reduced leakage paths and glitch-free output with reduced switching transients. Energy efficiency against static CMOS equivalent and better speed performance against 2N2P, 2N2N2P, PFAL and IPGL equivalent circuits are proved. By the use of post-layout simulations of multi-bit adder and multiplier circuits adopted through full-custom circuit design, the DCPAL achieves adiabatic gain values in the range of 20.85 at 100 MHz power clock frequency to 9.88 at 500 MHz against the static CMOS equivalent 8-bit Wallace tree multiplier circuit. Energy saving of 50% and 45% is achieved against optimized 2N2N2P and PFAL 8-bit multiplier circuits at 500 MHz, and energy saving against these circuits enhances further at higher frequencies. Copyright © 2008 American Scientific Publishers All rights reserved.

Journal	Data powered by TypesetLecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications
Publisher	Data powered by TypesetSpringer Singapore
ISSN	1876-1100
Open Access	No