Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This will significantly reduces the power dissipation. Various TSPICE simulation with different input sequences is done. The design has been simulated using Tanner 13.0 EDA tool with 0.25 μm technology. © 2013 IEEE.

Sakthivel S M

Electronics

School of Electronics Engineering

Chennai Campus

Noble G

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2013 International Conference on Communication and Signal Processing

Power consumption has a vital role in VLSI design technology for all time. One competence to attain the ultra-low power demand is to perform the logic gates in subthreshold region in digital field. The desire for low power consuming devices is elevating rapidly and the adiabatic logic style is an attractive solution. Adiabatic logic is a victorious resemble for static CMOS design when it appears to ultra-low-power energy consumption. Fortune head way like the remarkable dwindling of the lower limit for feature size as well as regime change in micro-electronics ideas will change the gate level savings procured by adiabatic logic which benefits from future devices. It is not easily influenced or effected to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Significant attentiveness also remains on the suitable production of the given power-clock signal. This informal regularized zigzag power supply can be used to save energy in short inactive times by disconnecting circuits. In this paper, we would like to analyze and to implement subthreshold adiabatic logic design under 180nm technology node using CADENCE - Virtuoso. © 2018 IEEE.

2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS)

Analysis and Implementation of Subthreshold Adiabatic Logic Design for Ultralow-Power Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Design of Sequential Elements for Low Power Clocking System

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

Dual-edge triggered storage elements and clocking strategy for low-power systems

High-performance and low-power conditional discharge flip-flop

A novel flip-flop design for low power clocking system

Journal	Data powered by Typeset2013 International Conference on Communication and Signal Processing
Publisher	Data powered by TypesetIEEE
Open Access	No