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A novel flip-flop design for low power clocking system
Noble G,
Published in IEEE
Pages: 627 - 631
Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This will significantly reduces the power dissipation. Various TSPICE simulation with different input sequences is done. The design has been simulated using Tanner 13.0 EDA tool with 0.25 μm technology. © 2013 IEEE.
About the journal
JournalData powered by Typeset2013 International Conference on Communication and Signal Processing
PublisherData powered by TypesetIEEE
Open AccessNo