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A novel method for design and implementation of low power, high stable SRAM cell
Ashish kumar sharma,
Published in IEEE
Pages: 112 - 116
SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %. © 2017 IEEE.
About the journal
JournalData powered by Typeset2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)
PublisherData powered by TypesetIEEE
Open Access0