SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %. © 2017 IEEE.

Ravi V

Electronics

School of Electronics Engineering

Chennai Campus

Ashish kumar sharma

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

A novel method for design and implementation of low power, high stable SRAM cell

2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)

Due to the continuous miniaturization in the size and increase in the complexity of the SRAM circuit causes the SRAM memory more prone to failure due to variations in process parameters which significantly affect and acutely degrading the output of SRAM. To enhance the consistent performance and firmness of SRAM towards parametric failures, fault detection mechanism based on various different algorithms is used to call built in Self-Test. In this paper a different circuit is implemented for the detection of faults based on the transient condition during the write operation of SRAM cell which has the self in test ability. Effectiveness of developed Built in Self-Test circuit is presented in this paper. Simulations are performed against the introduced fault in 6T SRAM Cell. The cadence virtuoso tool is used to design the SRAM cell, differential amplifier level shifter and comparator circuit. All the circuit designed with 180nm technology. © 2016 IEEE.

2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Built in self-test scheme for SRAM memories

Objectives: The objective is to find the optimum SNM of SRAM and then a BIST architecture is designed and implemented to test the SRAM cells varying the voltage of the bit lines. Methods/Analysis: In this paper we use a detection technique which is digitally programmable to detect the defective SRAM cells by using some additional set of SRAM cells to change the bitline voltage and then apply stress to the CUT. Findings: By using this programmable detection technique, cells can be tested even after the fabrication and accordingly one can find out the bit line voltages at which even weak and bad cells can be made useful. Improvement: The main advantage of programmability is that we can maintain considerable tradeoffbetween test yield and quality. The results at the end will justify the effectiveness of the BIST architecture.

Indian Journal of Science and Technology

Design and Development of BIST Architecture for Characterization of S-RAM Stability

Background/objectives: Built in Self Test Architectures are used for the online or offline testing of the digital circuits and can be operated both in normal as well as test mode. So the objective is to test the circuit under test in online mode with less concurrent test latency and less area overhead. Methods/Statistical Analysis: In the case of normal mode the time required for testing becomes undesirable parameter so here we prefer offline testing method with concurrent approach which is also monitoring the window at the input by applying input vectors considering circuit under test as most important part of the processor which is arithmetic logic unit. Findings: The particular locations of the input vectors are stored in the latches which worked as the memory elements and this proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90. Application/Improvement: The proposed scheme is comparable with the same architecture, considering TPG as LFSR (Linear Feedback Shift Register) and counter.

Built in Self Test Architecture using Concurrent Approach

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

Design of BIST using Self-Checking Circuits for Multipliers

Background: Research shows that the health care cost per capita have grown 2.4 percent faster than the gross domestic product (GDP) since 1970. The aim of this paper is to present a useful model of wireless system that can combine both hardware and software environments and it can also integrate with other technologies or infrastructure at a low cost, which can be used for the patient monitoring system. Methods: The biomedical sensor which is attached to the patient, will read analog data. The recorded data will be converted digitally by using Analog to Digital Converter (ADC) and a FPGA transmitter will be used to send this data to Phase Shift Keying (PSK) transmitter. The modulated data will be received by PSK receiver and another FPGA receiver will be used to get the data back on the system. For behavioural modelling Verilog hardware descriptive language is used to provide a high level abstraction and language constructions. And the Simulink software is used to provide a high-level mathematical modelling condition for digital communication system which can be used for the verification and algorithm development.The important modules implemented for the transmitter and receiver FPGA are bus interfacing, compression and the data framing. Findings: A short range wireless health monitoring wireless system is modelled by using a mixed software and hardware simulation environment.At all the stages of the hardware and software designs, different types of languages like Verilog HDL codes and MATLAB used to verify the operation of the modules. The behavioural HDL designed of the FPGA transmitter and receiver will be interfaced with the RF Simulink models of PSK transmitter and receiver by using System Generator (Sysgen) tool that acts as the converter simulator. A realistic design model of health monitoring system is implemented which can be used for future hardware design. Compression and framing are the two main operations used in the transmitter side. Data compression is implemented by Run-Length Encoding method and for data framing high data link control protocol has been used. The unique features of this models simulation are low cost, less complexity, low power dissipation and efficient data transmission. Finally the FPGA based healthcare system allows us to change the design configurations or up gradation of the system based on the requirements. Conclusion: In this paper distributed simulation approach is used for designing the health monitoring system which allows checking the specification of design at all the stages. Simulation by HDL and Simulink mixed models in not the objective of this work, but to prove that realistic design is possible for future health care system design.

Journal	Data powered by Typeset2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)
Publisher	Data powered by TypesetIEEE
Open Access	0