With advancement in technology, higher level integration is coming to fore which demands components with high performance and efficiency in time to market. In VLSI domain, layout design is quite a lengthy process. Spiral inductor being one of the crucial components in RFIC design needs to depict high performance and design flexibility. Implementation of parameterized cells (PCells) for modeling on-chip spiral inductors overcomes this issue. PCells design proves quite flexible and less time consuming compared to classical design approach of inductor. In this paper, an efficient PCell design technique for automatic layout generation is presented for on chip spiral inductor using Cadence SKILL scripts. To support the concept defined, PCell design for automatic layout generation of square, hexagonal and octagonal spiral inductor are designed using SKILL script in Virtuoso. The spiral inductor characteristics are further validated through EM simulations using ADS Momentum. © 2017 IEEE.