With advancement in technology, higher level integration is coming to fore which demands components with high performance and efficiency in time to market. In VLSI domain, layout design is quite a lengthy process. Spiral inductor being one of the crucial components in RFIC design needs to depict high performance and design flexibility. Implementation of parameterized cells (PCells) for modeling on-chip spiral inductors overcomes this issue. PCells design proves quite flexible and less time consuming compared to classical design approach of inductor. In this paper, an efficient PCell design technique for automatic layout generation is presented for on chip spiral inductor using Cadence SKILL scripts. To support the concept defined, PCell design for automatic layout generation of square, hexagonal and octagonal spiral inductor are designed using SKILL script in Virtuoso. The spiral inductor characteristics are further validated through EM simulations using ADS Momentum. © 2017 IEEE.

Kumaravel S

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Sobhana Tayenjam

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)

A High Performance Switchable Multiband Inductor Structure for LC-VCOs

18th International Symposium on VLSI Design and Test

Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors

The on-chip planar spiral inductors having variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q). In this paper, we present an efficient parameterized cell (pcell) design in cadence using SKILL scripts for automatic layout generation of these complex, high-Q, variable W&S spiral inductors comprising of single ended and symmetric structures with rectangular, hexagonal, octagonal and circular spirals. Electromagnetic simulations are performed on the inductor layouts generated using the developed pcells. The constant W&S and variable W&S spiral inductor structures are fabricated in a 0.18 μm silicon on insulator process. Measurements show ∼25% improvement in the quality factor of variable W%S spiral inductors compared to their constant W&S counterparts and also validates the proper operation of the developed inductor parameterized cells. The presented variable W&S inductor pcell significantly reduces the layout design time of RF circuit designers and also helps in the design automation of these complex inductor structures to boost their own performance and the RF circuits as well. © 2014 IEEE.

IEEE MTT-S International Microwave and RF Conference 2014, IMaRC 2014 - Collocated with Intemational Symposium on Microwaves, ISM 2014

A parameterized cell design for high-Q, variable width and spacing spiral inductors

IEEE Transactions on Electron Devices

Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology

2007 IEEE International SOI Conference

Integrated Inductors in HR SOI CMOS technologies: on the economic advantage of SOI technologies for the integration of RF applications

A PCell design methodology for automatic layout generation of spiral inductor using skill script

Journal	Data powered by Typeset2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
Publisher	Data powered by TypesetIEEE
Open Access	0