A threshold voltage model based on the solution of the three-dimensional (3-D) Poisson’s equation for an undoped triple-gate (TG) fin-shaped field-effect transistor (FinFET) with localized interface trapped charge is presented in this paper. Such localized interface charge created by either hot carrier injection or bias temperature instability degrades the threshold voltage and thereby the overall performance of FinFET devices. The proposed model considers the location of the interface traps and the length of the damaged region. The potential distribution and the threshold voltage of the TG FinFET obtained from the model are compared with data from technology computer-aided design simulations, which validates the model for different device dimensions, interface trapped charge densities, damaged region lengths, and drain biases. The results show that the variation of the threshold voltage mainly depends on the length of the damaged region and the thickness of the oxide but is independent of the fin width and height. Furthermore, short-channel effects such as threshold voltage roll-off and drain-induced barrier lowering are investigated, considering both positive and negative interface traps. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.

Bindu B

Electronics

School of Electronics Engineering

Chennai Campus

Sriram S.R

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Journal of Computational Electronics

An analytical model of threshold voltage fluctuations due to random discrete traps at Si/SiO2 interface and in gate oxide regions for undoped double-gate (DG) MOSFET with high-k/SiO2 gate dielectric stack is presented in this paper. The model is derived based on the solution of 2-D Poisson's equation considering both position and number fluctuation of traps. The distribution of traps at the Si/SiO2 interfaces and in both gate oxide regions in double-gate structure are obtained using the bivariate Poisson distribution. The impact of interface and oxide traps over the threshold voltage are analyzed separately and together for the samples of 500 devices. The results from the model are verified using 2-D TCAD simulation results for different trap position, trap density, device dimension and drain bias. Even though the variability due to traps present in the gate oxide is comparatively lesser than the interface traps, the effect of oxide traps located in the interfacial layer (SiO2) cannot be neglected. The device variability increases with the consideration of both interface and oxide traps simultaneously and the threshold voltage fluctuations (ΔVTH) reach maximum of 90 mV. The proposed model takes less computational time for the calculation of threshold voltage fluctuations due to discrete traps compared to the atomistic simulations and thus it is suitable for circuit simulation. © 2019 Elsevier Ltd

Microelectronics Reliability

Analytical modeling of random discrete traps induced threshold voltage fluctuations in double-gate MOSFET with HfO2/SiO2 gate dielectric stack

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed. © 2017, Springer Science+Business Media, LLC.

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL. © 2016 Elsevier Ltd. All rights reserved.

Journal	Data powered by TypesetJournal of Computational Electronics
Publisher	Data powered by TypesetSpringer Science and Business Media LLC
ISSN	1569-8025
Open Access	No