The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 nm CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that considers the device electrostatics is necessary to predict and mitigate these soft errors in VLSI circuits. In this article, a physics-based bias-dependent model is developed to determine the SET pulse width of a double-gate (DG) CMOS inverter with the heavy-ion strike on OFF state NMOS. The output voltage perturbations due to ion strike in the CMOS inverter and the SET pulse width model are derived from the bias-dependent SET current model previously reported. The variations in the output voltage of the inverter and the pulse width obtained from the developed model for different Linear Energy Transfer (LET), supply bias, strike positions, device dimensions, and load capacitances are validated with TCAD mixed-mode simulations. © 2001-2011 IEEE.