Presently, comparators have become indispensible in the design of Analog to Digital Converter (ADC) blocks. This work focuses on analyzing, comparing the different works reported on dynamic comparator design from conventional to contemporary needs. This work also advocates the best comparators suitable for different applications based on different parameters. The circuit design with appropriate mathematical design for different comparators was carried out in detail highlighting their pros and cons. Simulation of the reviewed circuits was carried out using gpdk 90nm technology in Cadence environment. The proposed design shows better efficiency as it's delay has been improved by at least 55% as compared to the other designs. © 2019 IEEE.