Floating point multiplication is one of the most frequently used arithmetic operation, but the high memory requirement and speed requirement of the IEEE-754 standard floating point multiplier prohibits its implementation in many systems which requires fast computing. Hence floating point multiplication becomes one of the main research areas. This research work aims for developing a new floating point architecture which reduces computation time, area and the power consumption when compared to many existing floating point multiplier. After the extensive literature survey, the new architecture has been identified which took Computation Sharing High speed Multiplier [CSHM] and Karatsuba algorithm as base architecture’s. This new architecture may reduce the area, power and increase speed further compared to existing CSHM based multipliers by replacing normal multiplication of alphabet set of precomputers unit of CSHM into multiplication of Karatsuba algorithm. The new developed architecture will be having the advantage of both CSHM as well as karatsuba algorithm. The semi custom flow of above proposed architecture will be carried out in cadence® in 180nm technology. © 2018, Institute of Advanced Scientific Research, Inc.. All rights reserved.