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Book Chapter
A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic ModulePublished in Springer Singapore
2018
Pages: 62 - 68
Topics: Flip-flop (58)%58% related to the paper, Node (circuits) (57)%57% related to the paper and Electronic circuit (53)%53% related to the paper
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About the journal
| Journal | Data powered by TypesetSoft Computing Systems Communications in Computer and Information Science |
|---|---|
| Publisher | Data powered by TypesetSpringer Singapore |
| ISSN | 1865-0929 |
| Open Access | 0 |
Authors (1)
Satheesh Kumar S- ASIC implementation of high speed pipelined DDR SDRAM controller
- Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS
- A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module
- SEU hardened DFF and 4 bit johnson counter using quatro latch in 45 nm technology
