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A source/drain-on-insulator structure to improve the performance of stacked nanosheet field-effect transistors
V. Jegadheesan,
Published in Springer
Volume: 19
Issue: 3
Pages: 1136 - 1143
For continued scaling with silicon, the stacked nanosheet field-effect transistor (SNSH-FET) is considered to be a major candidate for sub-7-nm technology. The radiofrequency (RF)/analog performance of a three-channel SNSH-FET is studied herein and benchmarked against a fin-shaped field-effect transistor (FinFET) at 7-nm technology and having the same footprint on the wafer. In the existing SNSH-FET on a bulk substrate, the source/drain junction formed on the bulk substrate contributes extra capacitance. An SNSH-FET structure with a source/drain-on-insulator (SDOI) configuration is presented herein, incorporating an extra channel (channel 4) on the bulk. Channel 4 has a supersteep retrograde (SSR) doping profile, which is achieved by placing a 10-nm-thick lightly doped silicon layer (SSR buffer layer) on the ground plane or a punchthrough-stopper (PTS) doped Si substrate. The parasitic source/drain junction capacitance and leakage under channel 4 are alleviated by growing a 10-nm-thick insulator layer before the in situ doped source/drain epiregion (a configuration referred to as SDOI). The presented structure has the same capacitance as the existing three-channel SNSH-FET on a PTS-Si substrate but with a 6% enhanced drive current, thereby achieving an improvement in terms of the delay and RF/analog performance. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.
About the journal
JournalData powered by TypesetJournal of Computational Electronics
PublisherData powered by TypesetSpringer