A unified model for gate capacitance-voltage characteristics of Si/SiGe heterostructure pMOSFETs is presented. This model is applicable to buried-channel, surface-channel, and dual-channel Si/SiGe heterostructure pMOSFETs. The results from the model are compared with the experimental results and are found to be in excellent agreement. A simple and accurate method for the extraction of parameters such as the valence band offset, Si cap layer thickness, threshold voltages, and substrate doping is also presented in this paper. © 2007 IEEE.

Bindu B

Electronics

School of Electronics Engineering

Chennai Campus

N. DasGupta

A. DasGupta

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

A Unified Model for Gate Capacitance–Voltage Characteristics and Extraction of Parameters of Si/SiGe Heterostructure pMOSFETs

IEEE Transactions on Electron Devices

A unified model for gate capacitance-voltage characteristics and extraction of parameters of Si/SiGe heterostructure pMOSFETs

Journal	IEEE Transactions on Electron Devices
ISSN	00189383