Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS'89 benchmark circuits' shows efficiency of the work in terms of reduction in test power. © 2013 IEEE.

Sivanantham S

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

John R.T

Sreekanth K.D

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Adaptive Low Power RTPG for BIST based test applications

2013 International Conference on Information Communication and Embedded Systems (ICICES)

This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used. © 2013 IEEE.

2013 International Conference on Computer Communication and Informatics

Adaptive test clock scheme for low transition LFSR and external scan based testing

In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.

2012 International Symposium on Electronic System Design (ISED)

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.

Journal	Data powered by Typeset2013 International Conference on Information Communication and Embedded Systems (ICICES)
Publisher	Data powered by TypesetIEEE
Open Access	0