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Adaptive test clock scheme for low transition LFSR and external scan based testing
, Gopakumar G, Pandey A, Paikada M.J.
Published in IEEE
This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used. © 2013 IEEE.
About the journal
JournalData powered by Typeset2013 International Conference on Computer Communication and Informatics
PublisherData powered by TypesetIEEE
Open Access0