This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used. © 2013 IEEE.

Sivanantham S

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Gopakumar G

Pandey A

Paikada M.J.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

&nbsp;

&nbsp;

VIT University

Adaptive test clock scheme for low transition LFSR and external scan based testing

2013 International Conference on Computer Communication and Informatics

This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

Fulltext

International Journal of Engineering & Technology

Test Data Compression with Alternating Equal-Run-Length Coding

Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS'89 benchmark circuits' shows efficiency of the work in terms of reduction in test power. © 2013 IEEE.

2013 International Conference on Information Communication and Embedded Systems (ICICES)

Adaptive Low Power RTPG for BIST based test applications

In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.

2012 International Symposium on Electronic System Design (ISED)

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

This paper presents a new approach to reduce both test power and test data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's by observing the effect of each X bit on the shift transition. The shift power and compression rate depends on the percentage of X bits present in the pattern. After filling the X-bits for shift power reduction, the patterns are compressed based on shifted alternating frequency directed run-length coding, which is suitable for encoding pre-computed test set of embedded cores in System-on-Chip(SoC). The experimental results on ISCAS'89 benchmark circuits show that our scheme provides better compression efficiency as well as significant reduction in test power.

2012 International Conference on Advances in Computing and Communications

Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme

This paper proposes a novel approach for reducing the shifting and capture power by a fan-out aware modified adjacent X-filling technique. This approach reduces the time complexity and number of iterations in addition to the reduction of test power. Experimental results obtained from ISCAS'89 circuits are compared with existing techniques prove that the proposed ATPG methodology is suitable to test the scan based system-on-chip architecture with reduced testing power.

Journal	Data powered by Typeset2013 International Conference on Computer Communication and Informatics
Publisher	Data powered by TypesetIEEE
Open Access	0