Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True Single Phase Clocking (TSPC), Limited Switch Dynamic Logic (LSDL) and Pseudo Dynamic Buffer (PDB). The PDB structure reduces the dynamic power to a greater extent, without increase in the number of transistors. Findings: The design of Arithmetic and logical units using PDB is presented in the paper for validating the claim. Conclusion: This paper details the design of an ALU using PDB based domino methodology. The PDB based domino logic ALU demonstrates an average power 11.86 mw with a delay of 152.75 ps. Simulations are carried using Cadence® Virtuoso with 180nm technology library file. © 2017 IEEE.