In this paper, we proposed a new design of hybrid adder for area-efficient 32-bit floating point multiplier. By combining conventional ripple carry adder (RCA) and Wallace tree adder for adding Generated Partial Products (GPPs), the speed can be improved. Toom-3 multiplication method applied on 24×24 mantissa multiplier with a reduced complexity of (n 1.465 ). Pre-determined Partial Products Generation (3PG) methods reduce the height of the GPPs to (N/3)/4 for N=24-bit unsigned operands. This is a contrast to Modified Booth Encoding (MBE) GPPs reduction height of N/2. This reduction can use to save area. The design is synthesized on TSMC 0.13 μm CMOS with 62% less area when compared to MBE based FP multiplier.
|Journal||Data powered by Typeset2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)|
|Publisher||Data powered by TypesetIEEE|