In this paper, we proposed a new design of hybrid adder for area-efficient 32-bit floating point multiplier. By combining conventional ripple carry adder (RCA) and Wallace tree adder for adding Generated Partial Products (GPPs), the speed can be improved. Toom-3 multiplication method applied on 24×24 mantissa multiplier with a reduced complexity of (n&nbsp;1.465&nbsp;). Pre-determined Partial Products Generation (3PG) methods reduce the height of the GPPs to (N/3)/4 for N=24-bit unsigned operands. This is a contrast to Modified Booth Encoding (MBE) GPPs reduction height of N/2. This reduction can use to save area. The design is synthesized on TSMC 0.13 μm CMOS with 62% less area when compared to MBE based FP multiplier.

Sivanantham S

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

J. Jean Jenifer Nesam

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

Background: Floating Point (FP) multiplication has found its importance in many microprocessors but it is very difficult to implement on FPGA because of its complicated internal computation. Methods: We investigate partial product (PP) reduced FP multiplication based on Radix-4 Booth Encoded Algorithm (BEA). Radix-4 BEA reduces the number of PP generation by half. PP reduction performed in three steps such as Grouping bits (3-bit for each group), Encode the group and PP calculation for each group. Findings: The investigation results show that Radix-4 BEA works perfectly on signed multiplication and unsigned (FP mantissa) multiplication needs some extra consideration. Radix-4 BEA grouping multiplier bits need overlapping one bit from both adjacent group that limits block and parallel processing. 2's complement calculation and sign extension essential for PP generation that increases the resource utilization. In this paper, 32 bit improved FP multiplication based on classical recoding and parallel processing method is proposed. Classical recoding reduces PP generation by half without overlapping, sign extension and 2's complement. 24 bit mantissa split into blocks (8 bit each) and each block is recoded using classical recoding algorithm and all blocks are performed in parallel. Applications: The experimental results show that our proposed design runs with high frequency with less resource utilization and suitable for signal processing applications.

Fulltext

Indian Journal of Science and Technology

An Efficient Single Precision Floating Point Multiplier Architecture based on Classical Recoding Algorithm

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An area-efficient 32-bit floating point multiplier using hybrid GPPs addition

Journal	Data powered by Typeset2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
Publisher	Data powered by TypesetIEEE
Open Access	No