Various physical layer protocols are employed to encode information bits in short range wireless communication technologies. In this paper, we propose a multimode hardware architecture for a digital baseband encoder which incorporates Manchester, Differential Manchester and FM0 codes. These codes help in achieving good DC balance thereby improving signal reliability. Alternating Manchester with Differential Manchester for different intervals of time improves security at the physical layer level. This work aims at efficient integration of hardware components for the three coding modes. This hybrid architecture has a hardware utilization ratio of 100%. The design has been implemented in Xilinx Virtex 5 FPGA. This multimode encoder operates at a maximum frequency of 434 MHz. The power consumption is 34 mW at 434 MHz. When compared with the similarity-oriented logic simplification (SOLS) based integrated FM0/Manchester encoder, this encoder poses the advantage of an extra encoding operation-Differential Manchester encoding despite a slight increase in area and power. © 2016 IEEE.