This paper includes the design of efficient double precision floating-point multiplier using radix-4 Modified Booth Algorithm (MBE) and Dadda Algorithm. This hybrid multiplier is designed by using the advantages in both the multiplier algorithms. MBE has the advantage of reducing partial products to be added. Dadda scheme has the advantage of adding the partial products in a faster manner. Our main objective is to combine these two schemes to make the multiplier design power efficient and area efficient. The floating-point multiplier is designed using Verilog HDL. The design is simulated using Altera ModelSim and synthesized using Cadence RTL compiler in TSMC 45 nanometre technology. It is found that multiplier has reduced power and area and it consumes 4619.23 μW and 34880 2μm2. © 2005 - 2014 JATIT & LLS. All rights reserved.