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An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, Fp
T. Kudithi,
Published in John Wiley and Sons Ltd
Volume: 48
Issue: 8
Pages: 1256 - 1273
Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, (Formula presented.). This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field (Formula presented.) and (Formula presented.), respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs. © 2020 John Wiley & Sons, Ltd.
About the journal
JournalData powered by TypesetInternational Journal of Circuit Theory and Applications
PublisherData powered by TypesetJohn Wiley and Sons Ltd