This brief presents an improved reconfigurable finite impulse response (FIR) filter architecture using binary common subexpression elimination (BCSE) algorithm for multistandard wireless receiver applications such as spectrum sensing and channelization. Detecting the presence of primary users and the ability to find white spaces in the licensed spectrum are the key enablers of the opportunistic communication. Filter bank based spectrum sensing employs a bank of FIR filters to extract the individual channel information from the received wideband input signal and to detect the spectrum occupancy by comparing each subband energy with a specific threshold. In this work, a novel architecture of constant shift method (CSM) based multiplier using the 2-bit BCSE algorithm for reconfigurable FIR filter is proposed, which can be employed in filter bank based spectrum sensing applications. This paper analyzes the implementation of 18-tap and 20-tap FIR filters using the proposed CSM multiplier in terms of hardware resources, speed and power consumption. The proposed filter architecture is realized on Application Specification Integrated Circuits (ASIC) platform using SAED90nm CMOS technology. The synthesis results of the proposed FIR filter shows reduction of 67%, 71% in area delay product (ADP) and 71%, 72% in power delay product (PDP) for 18-tap and 20-tap FIR filters, respectively compared to the 3-bit BCSE technique. Likewise, it achieves reduction of 31%, 34% in ADP and 34%, 37% in PDP, respectively compared to the existing 2-bit BCSE algorithm based reconfigurable FIR filter implementation. Copyright © 2015 American Scientific Publishers All rights reserved.