Profiles
Research Units
Publications
Sign Up
Faculty Login
X
Journal Article
Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic
Chitra E
,
Vigneswaran T
,
Malarvizhi S.
Published in Springer Science and Business Media LLC
2018
DOI:
10.1007/s11277-018-5375-4
Volume: 102
Issue: 4
Pages: 3413 - 3425
Request full-text
Cite
Content may be subject to copyright.
Figures & Tables (12)
Citations (1)
References (24)
Journal Details
Authors (1)
About the journal
Journal
Data powered by Typeset
Wireless Personal Communications
Publisher
Data powered by Typeset
Springer Science and Business Media LLC
ISSN
0929-6212
Open Access
0
Authors (1)
Vigneswaran T
Electronics
School of Electronics Engineering
Chennai Campus
Recent publications
FPGA Implementation of Hiding Information using Cryptography
Performance Analysis of Real Time Operating System with General Purpose Operating System for Mobile Robotic System
An Efficient Low Power and High Speed Distributed Arithmetic Design for FIR Filter
Low Power 64 Point FFT Processor
Get all the updates for this publication
Follow