Power consumption has a vital role in VLSI design technology for all time. One competence to attain the ultra-low power demand is to perform the logic gates in subthreshold region in digital field. The desire for low power consuming devices is elevating rapidly and the adiabatic logic style is an attractive solution. Adiabatic logic is a victorious resemble for static CMOS design when it appears to ultra-low-power energy consumption. Fortune head way like the remarkable dwindling of the lower limit for feature size as well as regime change in micro-electronics ideas will change the gate level savings procured by adiabatic logic which benefits from future devices. It is not easily influenced or effected to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Significant attentiveness also remains on the suitable production of the given power-clock signal. This informal regularized zigzag power supply can be used to save energy in short inactive times by disconnecting circuits. In this paper, we would like to analyze and to implement subthreshold adiabatic logic design under 180nm technology node using CADENCE - Virtuoso. © 2018 IEEE.