Profiles
Research Units
Publications
Sign Up
Faculty Login
X
Proceedings Article
ASIC flow implementation over multi clock processor block on 32 nm Node
Nikhil Pundlik Pathrabe
,
Rajeev Pankaj Nelapati
Published in IEEE
2017
DOI:
10.1109/icmdcs.2017.8211607
Request full-text
Cite
Content may be subject to copyright.
References (6)
Journal Details
Authors (1)
About the journal
Journal
Data powered by Typeset
2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
Publisher
Data powered by Typeset
IEEE
Open Access
0
Authors (1)
Rajeev Pankaj Nelapati
Department of Micro and Nanoelectronics
School of Electronics Engineering
Vellore Campus
Recent publications
Implementation of low-power multifunctional circuit for varying operand lengths
Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
ASIC flow implementation over multi clock processor block on 32 nm Node
Design and Performance Analysis of HybridSELBOX Junctionless FinFET
Get all the updates for this publication
Follow