This paper deals with design and implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN on ASIC. The architectures of both Autocorrelator and CORDIC are processed through ASIC Design flow to check for the timing of both setup as well as hold time for 130nm technology. Autocorrelator is designed to perform the autocorrelation of 128 samples each of 8 bits wide. The building blocks for the scheme have a 128×8 RAM, a multiplier, an accumulator and a counter. Matlab simulations are performed prior to the Verilog HDL coding to check if the functionality was achieved. Finally, an exhaustive test bench is written in Verilog HDL to simulate the design using ModelSim. Using Synopsys ASIC Design Flow, total area of 16609.6 μm2 and leakage power of 78.7 μW is achieved for the Autocorrelator. A fully pipelined CORDIC processor is designed with the help of Verilog HDL and synthesized. An exhaustive test bench is also written to simulate the functionality of the processor. The total cell area of 2558 μm2 and leakage power of 12 μW is achieved for the CORDIC architecture by using synopsis ASIC design flow. It is observed that, by using this proposed fast pipelined CORDIC architecture drastically increases area and power by increasing number of iterations and number of cells usage. © EuroJournals Publishing, Inc. 2009.