Bakshi A

Pandey S.S

Pradhan T

Dey R.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

ASIC implementation of DDR SDRAM Memory Controller

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)

Modern real-time embedded system must support multiple concurrently running applications. Double Data Rate Synchronous DRAM (DDR SDRAM) became mainstream choice in designing memories due to its burst access, speed and pipeline features. Synchronous dynamic access memory is designed to support DDR transferring. To achieve the correctness of different applications and system work as to be intended, the memory controller must be configured with pipelined design for multiple operations without delay. The main function of DDR SDRAM is to double the bandwidth of the memory by transferring data (either read operation or write operation) twice per cycle on both the falling and raising edges of the clock signal. The designed DDR Controller generates the control signals as synchronous command interface between the DRAM Memory and other modules. The DDR SDRAM controller supports data width of 64 bits and Burst Length of 4 and CAS (Column Address Strobe) latency of 2 and in this pipelined SRAM controller design, improvement of 28.57% is achieved in performance of memory accessing. The architecture is designed in Modelsim AlTERA STARTER EDITION 6.5b and Cadence (RTL complier and encounter). © 2014 IEEE.

International Conference on Information Communication and Embedded Systems (ICICES2014)

ASIC implementation of high speed pipelined DDR SDRAM controller

Advanced Materials Research

The Design of DDR-SDRAM Controller Based on Spartan3

International Conference on Nanoscience, Engineering and Technology (ICONSET 2011)

An innovative design of the DDR/DDR2 SDRAM compatible controller

Micron

Preface

Oxford Music Online

Medial cadence

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Journal	Data powered by Typeset2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)
Publisher	Data powered by TypesetIEEE
Open Access	0