Karatsubha based floating point multiplier has many attractive features like reduction in computation complexity and area but there is a problem of register complexity. In this paper, the modified KA algorithm based floating point multiplier is presented. In proposed multiplier single precision and double precision operations are supported. The iterative method which requires less hardware is used for DP operations which leads to reduction in power consumption. As the multiplication dominates the execution time, to overcome the problem in the proposed floating point multiplier for mantissa multiplication different algorithms are compared and best one is chosen which has less number of multiplications. This multiplier also handles underflow and overflow. In order to form a design Verilog is the description language and the tool used is modelsim Altera 10.1d (Quartus 11 13.0spl) and asic implementation is done in Synopsys tool. © 2018 IEEE.