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Asic implementation of high speed discrete integrator using vedic mathematics
Published in Blue Eyes Intelligence Engineering and Sciences Publication
Volume: 8
Issue: 8
Pages: 2246 - 2252

Vedic Mathematics is an ancient Indian mathematics which has unique technique for arithmetic computation. An ASIC based discrete integrator is designed in this paper. This is a novel architecture employs less numbers of multipliers when compared with the conventional one. The architecture could be used in 16-bit ALU. This research used cadence ncsim, rc compiler tool and 90nm technology for synthesis. This paper reveals the study of Vedic multiplier for 16, 32 & 64 bits which is totally unconventional method than shift add. A single architecture also can be used for squaring, cubing as well as Reimann Integral Theorem up to order 4. © BEIESP.

About the journal
JournalInternational Journal of Innovative Technology and Exploring Engineering
PublisherBlue Eyes Intelligence Engineering and Sciences Publication