Finite Impulse Response (FIR) filters are of great importance in Digital Signal Processing (DSP) systems since their characteristics are linear and are very useful for building high performance filters. This paper mainly focuses on the design of “Multiple Constant Multiplication” (MCM) operation of FIR filter using the "shift-Add" architecture. In order to reduce the total number of addition and shift operations, two algorithms known as Common Sub-expression Elimination (CSE) algorithm and Graph Based (GB) algorithm are described for bit-serial architecture. In this paper bit-parallel architectures have been proposed based on these algorithms. The design of MCM operation for obtaining the multiplication of the constants with the inputs for bit-serial and bit-parallel architectures has been done in the “CADENCE” software using verilog language. Synthesis of the proposed bit-parallel architecture is done in “CADENCE RTL Compiler” while the exact chip layout is generated using “SoC Encounter”. © 2016, International Journal of Pharmacy and Technology. All rights reserved.