This paper presents a brief on the implementation of reconfigurable shared LUT (look-up-Table) based Distributed Arithmetic (DA) for the higher order finite-impulse response (FIR) filters whose filter coefficients can be changed during run time. In this architecture all the multipliers and adders are replaced by the register banks, multiplexers and the shifters. The throughput rate of the design is increased by having shared LUTs instead of ROM in the DA FIR filter architecture. By implementing this concept in ASIC, the area, area delay product (ADP), minimum cycle period (MCP) and energy per sample are reduced when compare with the conventional DA architecture. The architecture supports 95 MHz sampling frequency. © 2017 IEEE.

Sri Adibhatla Sridevi

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Naga Jyothi Grande

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

International Journal of Speech Technology

High speed low area OBC DA based decimation filter for hearing aids application

IEEE Transactions on Circuits and Systems II: Express Briefs

Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic

IEEE Transactions on Circuits and Systems I: Regular Papers

A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering

ASIC implementation of shared LUT based distributed arithmetic in FIR Filter

Journal	Data powered by Typeset2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
Publisher	Data powered by TypesetIEEE
Open Access	No