This paper presents the quasi-adiabatic Asymmetrical Positive Feedback Adiabatic Logic (APFAL) for low power operation through energy recovery technique. The topology of a logic gate defines the logic effort and it determines the gate sensitivity. The APFAL strives to reduce the logic effort of one arm of the 2N2P latch which results in reduced values of adiabatic and non-adiabatic power components. The use of asymmetric complementary functional blocks in the sense-amplifier structure achieves this. Furthermore, the APFAL incurs reduced transients and minimized floating node problems. It is a diode-free and dual rail logic offering both the true and complementary outputs. It achieves significant reduction in switched capacitance resulting in faster response. Efficient energy recovery is achieved for frequency range of up to 500 MHz. The need for reduced interconnects and realization of less leakage are the added advantages. Validation is done through full-custom designed arithmetic circuits. Comparison with static CMOS and PFAL circuits are made to validate the design. In post-layout simulations, the 8-bit APFAL multiplier achieves an adiabatic gain of 14.91 at 100 MHz to 6.45 at 500 MHz against the static CMOS counterpart. Energy savings of 27% and 22.5% are achieved against the optimized PFAL 4-bit CLA and 8- bit multiplier equivalent circuits respectively, at 500 MHz. © 2010 IEEE.