Built-in Self-Test is a circuit embedded within the design to detect the faults in the System-on-a-Chip circuits. It shrinks the test application time and reduces the cost of external testing equipment. This paper presents a test pattern generation methodology for detection of transition faults using in-circuit arithmetic circuits. Arithmetic circuits are used for pattern generation which utilizes the accumulators in the design itself with the inclusion of additional control unit for pattern generation. This control unit controls the pattern generation circuit to reduce the transition power during testing and ensure better fault coverage. The main focus of this paper is to reduce the area overhead using arithmetic circuits and also to reduce the power of the test pattern generator. The proposed method can be made use in circuits that contains gray code converters. Experimental results show that the proposed technique has lower power consumption and lesser hardware compared to linear generators.