Due to the continuous miniaturization in the size and increase in the complexity of the SRAM circuit causes the SRAM memory more prone to failure due to variations in process parameters which significantly affect and acutely degrading the output of SRAM. To enhance the consistent performance and firmness of SRAM towards parametric failures, fault detection mechanism based on various different algorithms is used to call built in Self-Test. In this paper a different circuit is implemented for the detection of faults based on the transient condition during the write operation of SRAM cell which has the self in test ability. Effectiveness of developed Built in Self-Test circuit is presented in this paper. Simulations are performed against the introduced fault in 6T SRAM Cell. The cadence virtuoso tool is used to design the SRAM cell, differential amplifier level shifter and comparator circuit. All the circuit designed with 180nm technology. © 2016 IEEE.

Ravi V

Electronics

School of Electronics Engineering

Chennai Campus

Sharma A

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Built in self-test scheme for SRAM memories

2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %. © 2017 IEEE.

2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)

A novel method for design and implementation of low power, high stable SRAM cell

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

Indian Journal of Science and Technology

Design of BIST using Self-Checking Circuits for Multipliers

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

Design of BIST Architecture of 8×8 SRAM Testing using Transient Current Method

2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES

Built in self test architecture for testing SRAM using transient current testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Self-Repairing SRAM Using On-Chip Detection and Compensation

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell

Journal	Data powered by Typeset2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI)
Publisher	Data powered by TypesetIEEE
Open Access	0