Ganesan K

Department of Software and Systems Engineering

School of Information Technology and Engineering

Vellore Campus

Valli D

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

The European Physical Journal Plus

In this work, we demonstrate the use of a Field Programmable Gate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally study the synchronization between two time delayed systems. We illustrate two different experimental approaches - one is hardware co-simulation (using a Digilent Atlys with a Xilinx Spartan-6 FPGA) and the other is analog output (using a Terasic DE2-115 with an Altera Cyclone IV E FPGA). © 2014 EDP Sciences and Springer.

The European Physical Journal Special Topics

Synchronization in coupled Ikeda delay systems

In this paper, we show how chaotic time delay systems can be realized physically using a Field Programmable Gate Array (FPGA) platform. There are various analog realizations of chaotic delay differential equations (DDEs) Namajunas et al. (1995), Busarino et al. (2011), and Srinivasan et al. (2010). The disadvantage with the analog realization is the number of components required for realizing the delay (example: n operational amplifiers for an n-stage delay in Busarino et al. (2011)) and the inability to synthesize some nonlinear functions using analog electronics. For example, the Ikeda chaotic DDE (Ikeda and Matsumoto, 1987) involves a sine nonlinearity and this is difficult to synthesize using analog electronics. In fact, we are not aware of any electronic realization of the Ikeda DDE. © Springer Science+Business Media Dordrecht 2014.

Chaos, Complexity and Leadership 2012 Springer Proceedings in Complexity

Chaotic Time Delay Systems and Field Programmable Gate Array Realization

2008 Fifth International Conference on Computer Graphics, Imaging and Visualisation

Journal	Data powered by TypesetThe European Physical Journal Plus
Publisher	Data powered by TypesetSpringer Science and Business Media LLC
Open Access	0